"RISC-V" is the specification of the instruction-set defined by RISC-V International originating from UC Berkeley.

RISC-V's core instruction-set is quite reduced and completely refined. It has only those instructions that are essential, banishing all others to extensions.

This author has written assembly language for various microprocessors (6502, 80x86, PowerPC, ARM, etc) plus familiar with others such as Z-80, 68000, MIPS, etc. Once upon a time believed 68000 was the most elegant -- until advent of RISC-V. None of those were anywhere near to being as elegant, refined, logical, sensible, no-nonsense as RISC-V.

RISC-V extensions

First, since RISC-V standard extensions are optional, criticisms of them here are nullified. Proceeding anyway...

Subconscious mind of every computer architect thinks ultimate goal is for hardware to run an entire software program in one mega-complex instruction:

.align 1048576
FIREFOXBROWSER   R1, R2, R3, R4, ..................................., R262144

The temptation of CISC is irresistible...
...it always starts with thinking...
...if this instruction can do just one more operation...

Because of this temptation, RISC-V standard extensions are becoming a junk-yard for various experiments in CISC.

This author has criticized SIMD instructions. So have designers of RISC-V themselves. Yet SIMD standard extension is planned.

J extension for accelerating Java/JavaScript is precisely the sort of junk to keep out. Java is an extinct language from a dead patent troll, discredited years ago. JavaScript will still be slowed by many other factors (network, server load, etc). Probably this extension was intended for other interpreted languages also, but any RISC CPU should be fast enough. FORTH threaded-code ran fast enough on 1Mhz 6502 to be an alternative to writing assembly language.

future of RISC-V


This author predicts RISC-V very-very-very probably will supersede 80x86 and ARM. Its open-license should spark a competitive RISC-V CPU market. RISC-V probably will be the "industry-standard" CPU, similar to "IBM PC compatible", except Intel and ARM will be relegated instead of IBM (anyone remember IBM?).

Which design would be easier to build?
  ~300 pages : documentation of RISC-V core instructions
~2,700 pages : documentation of ARMv7 ArchRefMan
~5,100 pages : documentation of Intel 80x86 [2021/04]
~7,500 pages : documentation of ARMv8 ArchRefMan (only Lt Cmdr Data could read it all)

Much faster out-of-order implementations can be created with RISC-V. Most RISC-V core instructions do only one operation, which will simplify out-of-order execution (achieved with great complexity in 80686). Many 80x86 instructions compute FLAGS/CC in case followed by a conditional jump, but often no jump is present, so now the frequent effect of FLAGS/CC is creating dependencies across instructions, complicating out-of-order execution. FLAGS/CC wastes transistors, a PowerPC generation had a "wide" integer unit, only that one could compute FLAGS/CC. RISC-V solves all these problems by eliminating FLAGS/CC register, instead, RISC-V has compare-and-branch instructions.

And more energy-efficient implementations can be created with RISC-V. ARM's decoder has probably grown more complex than 80x86, since ARM's rate of whimsically creating/bloating/deprecating instruction-sets has surpassed 80x86.