ARM (positive commentary)

One of ARM's interesting features is (was) conditional instructions. An opcode field specifies a condition such as EQ or NE, then execution of instruction becomes conditional. IOW, instruction becomes a NOP if condition is false. So that eliminated a jump/branch instruction and pipe-line stall. Intel/HP borrowed this idea for Itanium, renaming it predication.

arm:
        CMP     R1, R2
        ADDEQ   R3, R4          # ADD or NOP

itanium:
        CMPEQ   P1, P0=R1, R2   # P1 is a predication register
(P1)    ADD     R3=R4, R5       # ADD or NOP

80x86:
        CMP     AX, BX
        JNE     over
        ADD     CX, DX
over:

ARM (negative commentary)

ARM began as a simple design influenced by 6502 and RISC. Gradually ARM is becoming a bigger bloated mess than even 80x86.

  • ~2,700 pages : documentation of ARMv7 ArchRefMan
    ~7,500 pages : documentation of ARMv8 ArchRefMan (only Lt Cmdr Data could read it all)
  • ARM doesn't have an instruction-set -- ARM has a multitude of instruction-sets
  • at least three 16-bit instruction-sets (Thumb, ThumbEE, Thumb2)
  • at least SIX FP instruction-sets (odd one is ARMv8.2-FP16)
  • at least two SIMD instruction-sets
  • at least one byte-code instruction-set (Jazelle)

As if eight versions { ARMv1,...,ARMv8 } weren't enough, now there's minor versions { ARMv8.1,...,ARMv8.6 }, then out to letter suffixes, ARMv8.6A (or ARMv8-A.6?).


future of ARM

[2021/06]

This author predicts 80x86 and ARM very probably will be superseded by RISC-V.